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FDSS2407 N-Channel Dual MOSFET
December 2004
FDSS2407 N-Channel Dual MOSFET
62V, 3.3A, 132m Features
62V, 132m, 5V Logic Level Gate Dual MOSFET in SO-8 5V Logic Level feedback signal of the drain to source voltage. Multiple devices can be wired "OR'd" to a single monitoring circuit input. Gate Drive Disable Input. Multiple devices controllable by a single disable transistor. Qualified to AEC Q101
General Description
This dual N-Channel MOSFET provides added functions as compared to a conventional Power MOSFET. These are: 1. A drain to source voltage feedback signal and 2. A gate drive disable control function that previously required external discrete circuitry. Including these functions within the MOSFET saves printed circuit board space. The drain to source voltage feedback function provides a 5V level output whenever the drain to source voltage is above 62V. This can monitor the time an inductive load takes to dissipate its stored energy. Multiple feedback signals can be wired "OR'd" together to a single input of the monitoring circuit. The gate disable function allows the device to be turned off independent of the drive signal on the gate. This function permits a second control circuit the ability to deactivate the load if necessary. It can also be wired "OR'd" allowing multiple devices to be controlled by a single open collector / drain control transistor.
Applications
Automotive Injector Driver Solenoid Driver
Internal Diagram
Source 1 Branding Dash
5 1 2 3 4
1 8
Drain 1
Gate 1
2
7
Gate Disable
SO-8 Pin 5 - Drain Feedback Output Pin 7 - Gate Drive Disable Input
Source 2
3
6
Drain 2
Gate 2
4
5
Drain FBK
(c)2004 Fairchild Semiconductor Corporation FDSS2407 Rev. A
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FDSS2407 N-Channel Dual MOSFET
MOSFET Maximum Ratings TA=25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TA = 25oC, VGS = 10V, RJA = 55oC/W) Continuous (TA = Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy ( Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 25oC, VGS = 5V, RJA = 55oC/W) 3.3 3.0 Figure 4 140 2.27 18 -55 to 150 A A A mJ W mW/oC
oC
Ratings 62 20
Units V V
Thermal Characteristics
RJA RJA RJA Pad Area = 0.50 in2 (323 mm2) (Note 2) Pad Area = 0.027 in (17.4 mm ) (Note 3) Pad Area = 0.006 in2 (3.87 mm2) (Note 4)
2 2
55 180 200
o o
C/W C/W
oC/W
Package Marking and Ordering Information
Device Marking 2407 Device FDSS2407 Package SO-8 Reel Size 330 mm Tape Width 12 mm Quantity 2500
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 5mA, VGS = 0V VDS = 15V, VGS=0V VDS = 15V, VGS=0V, TA=150oC VGS = 20V 62 1 250 100 A nA V
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 3.3A, VGS = 10V ID = 3.0A, VGS = 5V 1 0.099 0.115 3 0.110 0.132 V
Dynamic Characteristics
CISS COSS CRSS RG Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VGS = 0V to 5V VGS = 0V to 1V VDD = 30V ID = 3.3A Ig = 1.0mA VDS = 15V, VGS = 0V, f = 75kHz 300 140 16 8500 3.3 0.4 1.2 0.8 2.0 4.3 0.5 pF pF pF nC nC nC nC nC
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FDSS2407 N-Channel Dual MOSFET
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
(VGS = 10V) VDD = 30V, ID = 3.3A VGS = 10V, RGS = 47 630 1200 8700 3500 2700 18500 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 3.3A ISD = 1.7A ISD = 3.3A, dISD/dt = 100A/s ISD = 3.3A, dISD/dt = 100A/s 1.25 1.0 45 60 V V ns nC
Drain Feedback Characteristics
VFBK(Low) Feedback to Source Voltage VFBK(High) Feedback to Source Voltage VDS = 35V, RFBK-SOURCE =51K VDS = 62V, RFBK-SOURCE =51K 3.5 1 4.4 1.5 V V
Gate Drive Disable Characteristics
VDIS(High) VDIS(Low) Gate Drive Disable Input Voltage, Gate VGS = 5V, ID = 3.0A, TJ=25oC Enabled Gate Drive Disable Input Voltage, Gate VGS = VDS = 10V, ID 250A, Disabled TJ=150oC 3 0.4 V V
Notes: 1. Starting TJ = 25C, L = 42mH, IAS = 2.6A, VDD = 62V, VGS = 10V. 2. 55oC/W measured using FR-4 board with 0.50 in2 (323 mm2) copper pad at 1 second. 3. 180oC/W measured using FR-4 board with 0.027 in2 (17.4 mm2) copper pad at 1000 seconds. 4. 200oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
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FDSS2407 N-Channel Dual MOSFET
Typical Characteristics
1.2
TA = 25C unless otherwise noted
4
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A) 3
VGS = 10V
0.8
0.6
2 VGS = 5V
0.4
1 RJA = 55oC/W
0.2
0 0 25 50 75 100 (oC) 125 150 TA , AMBIENT TEMPERATURE
0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 ZJA, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
RJA = 55oC/W
0.1
PDM
t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 100 101 102 103
0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
200
RJA = 55oC/W
100
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
VGS = 5V
10
VGS = 10V
3
10-5
10-4
10-3
10-2
10-1 t, PULSE WIDTH (s)
100
101
102
103
Figure 4. Peak Current Capability
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FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) TA = 25C unless otherwise noted
100 10
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
STARTING TJ = 25oC
100s 10 1ms 10ms 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
STARTING TJ = 150oC
RJA =
55oC/W
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
15
15
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
TJ = 25oC ID, DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 10 VGS = 10V
VGS = 5V
ID , DRAIN CURRENT (A)
10
VGS = 3.5V
5 TJ = 150oC TJ = -55oC 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VGS , GATE TO SOURCE VOLTAGE (V)
5
VGS = 3V
0 0 0.5 1.0 1.5 2.0 2.5 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
240 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 210 ID = 3.3A 180
Figure 8. Saturation Characteristics
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
150
1.0
120
ID = 1A
VGS = 10V, ID = 3.3A 90 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) 0.5 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
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FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) TA = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 5mA
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6 -80
-40
0
40
80
120
160
0.9 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
6 FBK, FEEDBACK VOLTAGE (V) FBK voltage measured across a 51K load resistor. 5
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
1000
CISS = CGS + CGD C, CAPACITANCE (pF)
4 TJ = 150oC 3 TJ = 25oC 2 TJ = -55oC 1
COSS CDS + CGD 100
CRSS = CGD
VGS = 0V, f = 75kHz 0 20 30 40 50 60 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 10 0.1 1 VDS , DRAIN TO SOURCE VOLTAGE (V) 10 20
Figure 13. Feedback Voltage vs Drain to Source Voltage
500 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 3A
Figure 14. Capacitance vs Drain to Source Voltage
10 TJ = 150oC 8 VGS , GATE TO SOURCE VOLTAGE TJ = 25oC 6 TJ = -55oC 4 VGS = VDS ID = 250A
rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
400
300 TJ = 150oC 200 TJ = 25oC 100 TJ = 0 1 2 3 4 5 VDIS , GATE DISABLE VOLTAGE (V) -55oC
2
0 0 1 2 3 4 5 VDIS , GATE DISABLE VOLTAGE (V)
Figure 15. Drain to Source On Resistance vs Gate Disable Voltage
Figure 16. Gate to Source Voltage vs Gate Disable Voltage
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FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) TA = 25C unless otherwise noted
10 VDD = 30V VGS , GATE TO SOURCE VOLTAGE (V) 8
6
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 3.3A ID = 1A 0 2 4 Qg, GATE CHARGE (nC) 6 8
0
Figure 17. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 18. Unclamped Energy Test Circuit
Figure 19. Unclamped Energy Waveforms
VDS RL VDD Qg(TOT) VDS VGS VGS
VGS = 5V
+
VDD DUT Ig(REF) VGS = 1V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 20. Gate Charge Test Circuit
Figure 21. Gate Charge Waveforms
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FDSS2407 N-Channel Dual MOSFET
Test Circuits and Waveforms (Continued)
VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 22. Switching Time Test Circuit
VDS
Figure 23. Switching Time Waveforms
+
LM324
-
NC
VDISABLE DUT
Figure 24. Gate to Source Voltage vs Gate Disable Voltage
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FDSS2407 N-Channel Dual MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P DM = -----------------------------R JA
maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 25 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 79.9 + ------------------------------0.14 + Area
15
(EQ. 2)
(EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 26 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 79.9 + 15/(0.14+Area)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 25 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized
160 COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2
RJA (oC/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 25. Thermal Resistance vs Mounting Pad Area
IMPEDANCE (oC/W)
ZqJA, THERMAL
120
80
40
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
Figure 26. Thermal Impedance vs Mounting Pad Area
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FDSS2407 N-Channel Dual MOSFET
PSPICE Electrical Model
.SUBCKT FDSS2407 2 1 3 101 102 ; rev July 2004 Ca 12 8 1e-10 Cb 15 14 4e-10 Cin 6 8 2.8e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD LDRAIN Dplcap 10 5 DplcapMOD DPLCAP 5 DRAIN CGATE 9 20 5e-9 2 10 DDISABLE 20 101 DDISABLEMOD RLDRAIN DFBK1 104 103 DFBK1MOD RSLC1 RFBK1 DBREAK 51 DFBK2 7 104 DFBK2MOD RSLC2 103 DFBK3 104 102 DFBK3MOD 5 11 RFBK1 5 103 RFBK1MOD 13e3 51 ESLC DFBK1 RFBK2 104 7 RFBK2MOD 2.15e3 + 50 DBODY Ebreak 11 7 17 18 67.4 EBREAK 17 INJ FBK 104 RDRAIN 6 102 Eds 14 8 5 8 1 18 ESG 8 DFBK3 Egs 13 8 6 8 1 EVTHRES + 16 CGATE 21 + 19 Esg 6 10 6 8 1 MWEAK DFBK2 LGATE EVTEMP 8 Evthres 6 21 19 8 1 RGATE + 18 GATE 6 RFBK2 Evtemp 20 6 18 22 1 MMED 1 22 9 20 It 8 17 1 MSTRO RLGATE Lgate 1 9 1.8e-9 LSOURCE CIN Ldrain 2 5 1.0e-9 GATE SOURCE 8 7 3 Lsource 3 7 0.6e-9 DISABLE 101 RSOURCE RLgate 1 9 18 RLSOURCE DDISABLE RLdrain 2 5 10 S1A S2A RLsource 3 7 6 RBREAK 12 15 14 13 Mmed 16 6 8 8 MmedMOD 17 18 13 8 Mstro 16 6 8 8 MstroMOD RVTEMP S1B S2B Mweak 16 21 8 8 MweakMOD 13 19 CB Rbreak 17 18 RbreakMOD 1 CA IT + 14 + Rdrain 50 16 RdrainMOD 3.5e-2 VBAT 6 5 Rgate 9 20 RgateMOD 8.63e3 EGS 8 EDS 8 + RSLC1 5 51 RSLCMOD 1e-6 8 RSLC2 5 50 1e3 22 Rsource 8 7 RsourceMOD 5.3e-2 RVTHRES Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),3.5))} .MODEL DbodyMOD D (IS=1.1E-12 N=1.05 IKF=4e-1 RS=4.2e-2 TRS1=3e-4 TRS2=1.3e-6 + CJO=3.3e-10 TT=3e-8 M=0.38, XTI=3.5) .MODEL DbreakMOD D (RS=1 TRS1=1e-3 TRS2=-9e-6) .MODEL DplcapMOD D (CJO=1.97e-10 IS=1e-30 N=10 M=0.84) .MODEL DDISABLEMOD D (RS=30 IS=1e-15 BV=4.7 TBV1=-3e-4 TBV2=-3e-6 XTI=0) .MODEL DFBK1MOD D (IS=1e-15 BV=23.8 IKF=2 TBV1=-6e-4 TBV2=6e-6) .MODEL DFBK2MOD D (RS=1 IS=1e-30 BV=5.6 N=3.3 NBV=1) .MODEL DFBK3MOD D (RS=1 IS=1e-15 BV=4.2 NBV=2.5) .MODEL MmedMOD NMOS (VTO=1.7 KP=1.08 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e3) .MODEL MstroMOD NMOS (VTO=2 KP=14 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.5 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e4 RS=0.1) .MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-9e-7) .MODEL RdrainMOD RES (TC1=9e-3 TC2=2.7e-5) .MODEL RSLCMOD RES (TC1=2e-3 TC2=6e-6) .MODEL RsourceMOD RES (TC1=3e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-1.1e-3 TC2=-3.3e-6) .MODEL RvtempMOD RES (TC1=-1.6e-3 TC2=1e-7) .MODEL RFBK1MOD RES (TC1=-1.4e-3 TC2=1e-6) .MODEL RFBK2MOD RES (TC1=-1.4e-3 TC2=1e-6) .MODEL RgateMOD RES (TC1=-1.4e-3 TC2=1e-5) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-3.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-4.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-1.0) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
10 FDSS2407 Rev. A www.fairchildsemi.com
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FDSS2407 N-Channel Dual MOSFET
SABER Electrical Model
REV July 2004 template FDSS2407 n2,n1,n3,n101,n102 electrical n2,n1,n3,n101,n102 { var i iscl dp..model dbodymod = (isl=1.1e-12,nl=1.05,ikf=4e-1,rs=4.2e-2,trs1=3e-4,trs2=1.3e-6,cjo=3.3e-10,tt=3e-8,m=0.38,xti=3.5) dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-9e-6) dp..model ddisablemod = (rs=30, isl=1e-15,bv=4.7,tbv1=-3e-4,tbv2=-3e-6,xti=0) dp..model dfbk1mod = (isl=1e-15,bv=23.8,ikf=2,tbv1=-6e-4,tbv2=6e-6) dp..model dfbk2mod = (rs=1,isl=1e-30,bv=5.6,nl=3.3,nbv=1) dp..model dfbk3mod = (rs=1,isl=1e-15,bv=4.2,nbv=2.5) dp..model dplcapmod = (cjo=1.97e-10,isl=10e-30,nl=10,m=0.84) m..model mmedmod = (type=_n,vto=1.7,kp=1.08,is=1e-30,tox=1) m..model mstrongmod = (type=_n,vto=2,kp=14,is=1e-30,tox=1) m..model mweakmod = (type=_n,vto=1.5,kp=0.04,is=1e-30, tox=1,rs=0.1) m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-3.0) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.0,voff=-4.0) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.0,voff=-0.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-1.0) c.ca n12 n8 = 1e-10 c.cb n15 n14 = 4e-10 c.cin n6 n8 = 2.8e-10 c.cgate n9 n20 = 5e-9
10 RLDRAIN DBODY dp.dbody n7 n5 = model=dbodymod RSLC1 RFBK1 dp.dbreak n5 n11 = model=dbreakmod 51 dp.dplcap n10 n5 = model=dplcapmod RSLC2 103 dp.ddisable n20 n101 = model=ddisablemod ISCL DFBK1 dp.dfbk1 n104 n103 = model=dfbk1mod DBREAK 50 dp.dfbk2 n7 n104 = model=dfbk2mod INJ FBK 104 dp.dfbk3 n104 n102 = model=dfbk3mod RDRAIN 6 102 11 ESG 8 spe.ebreak n11 n7 n17 n18 = 67.4 DFBK3 EVTHRES + 16 CGATE spe.eds n14 n8 n5 n8 = 1 21 + 19 MWEAK DFBK2 spe.egs n13 n8 n6 n8 = 1 LGATE EVTEMP 8 RGATE + 18 GATE spe.esg n6 n10 n6 n8 = 1 6 RFBK2 EBREAK MMED 1 22 + spe.evthres n6 n21 n19 n8 = 1 9 20 MSTRO 17 spe.evtemp n20 n6 n18 n22 = 1 RLGATE GATE i.it n8 n17 = 1 DISABLE l.lgate n1 n9 = 1.8e-9 101 l.ldrain n2 n5 = 1.0e-9 DDISABLE l.lsource n3 n7 = 0.6e-9 S1A S2A 12 res.rlgate n1 n9 = 18 15 13 14 8 13 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 6 S1B S2B res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-9e-7 13 CB CA res.rdrain n50 n16 = 3.5e-2,tc1=9e-3,tc2=2.7e-5 + 14 + res.rgate n9 n20 = 8.63e3,tc1=-1.4e-3,tc2=1e-5 6 5 EGS EDS 8 res.rfbk1 n5 n103 = 13e3,tc1=-1.4e-3,tc2=1e-6 8 res.rfbk2 n104 n7 = 2.15e3,tc1=-1.4e-3,tc2=1e-6 res.rslc1 n5 n51 = 1e-6,tc1=2e-3,tc2=6e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.3e-2,tc1=3e-3,tc2=1e-6 res.rvthres n22 n8 = 1,tc1=-1.1e-3,tc2=-3.3e-6 res.rvtemp n18 n19 = 1,tc1=-1.6e-3,tc2=1e-7 CIN 8 RSOURCE RBREAK 17 18 RVTEMP 19 IT VBAT + 8 RVTHRES 22 18 7 LSOURCE SOURCE 3 RLSOURCE
LDRAIN DPLCAP 5 DRAIN 2
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 3.5)) } }
11 FDSS2407 Rev. A
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FDSS2407 N-Channel Dual MOSFET
SPICE Thermal Model
REV July 2004 FDSS2407T Copper Area =0.5 in2 CTHERM1 Junction c2 1.2e-4 CTHERM2 c2 c3 2e-3 CTHERM3 c3 c4 2e-2 CTHERM4 c4 c5 3.0e-2 CTHERM5 c5 c6 4e-2 CTHERM6 c6 c7 7e-2 CTHERM7 c7 c8 2e-1 CTHERM8 c8 Ambient 2.8
RTHERM1
th
JUNCTION
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM1 Junction c2 1.4 RTHERM2 c2 c3 2.0 RTHERM3 c3 c4 2.8 RTHERM4 c4 c5 9.0 RTHERM5 c5 c6 18.0 RTHERM6 c6 c7 26.0 RTHERM7 c7 c8 28.0 RTHERM8 c8 Ambient 29.0
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
SABER Thermal Model
Copper Area = 0.5 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =1.2e-4 ctherm.ctherm2 c2 c3 =2e-3 ctherm.ctherm3 c3 c4 =2e-2 ctherm.ctherm4 c4 c5 =3.0e-2 ctherm.ctherm5 c5 c6 =4e-2 ctherm.ctherm6 c6 c7 =7e-2 ctherm.ctherm7 c7 c8 =2e-1 ctherm.ctherm8 c8 tl =2.8 rtherm.rtherm1 th c2 =1.4 rtherm.rtherm2 c2 c3 =2.0 rtherm.rtherm3 c3 c4 =2.8 rtherm.rtherm4 c4 c5 =9.0 rtherm.rtherm5 c5 c6 =18.0 rtherm.rtherm6 c6 c7 =26.0 rtherm.rtherm7 c7 c8 =28.0 rtherm.rtherm8 c8 tl =29.0 }
RTHERM5
5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
AMBIENT
12 FDSS2407 Rev. A
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FDSS2407 N-Channel Dual MOSFET
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I15
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
13 FDSS2407 Rev. A
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